The development of integrated circuits requires many specialized software programs (tools) that perform certain analyses and data transformations. These analyses and data transformations provide the vehicle by which the designer develops, and proofs formalized descriptions of the integrated circuits design. These formalized descriptions can be used to manufacture the integrated circuits according to the design. The collection of these tools so that they enable a coherent design process is known as a design flow.
The field of circuit simulations has many design languages, simulators, and design programs available to circuit design engineers. One commonly utilized design language is the Verilog® (a registered trademark of Cadence Design Systems, Inc.).
Verilog® is a hardware description language that provides a means of specifying a digital system at a wide range of abstraction levels. The language supports the early conceptual stages of design with its structural level of abstraction. The language provides hierarchical constructs, allowing the designer to control the complexity of a description.
Other analysis tools have been developed around the Verilog® language, including fault simulators, and timing analyzers, and the language has provided input specification for some logic and behavioral synthesis tools. The language has been standardized as IEEE standard #1364-1995, and is described in detail in “The Verilog® Hardware Description Language,” by Donald E. Thomas and Phillip R. Moorby, and is incorporated herein by reference.
Analog circuits are commonly simulated by SPICE (Simulation Program with Integrated Circuit Emphasis), a commercially available software program for simulating analog circuits. SPICE frees engineers from the laborious, and often complex, time consuming tasks of analog circuit analysis. SPICE was originally developed by a team at the University of California at Berkeley and consists of a set of powerful algorithms for a wide range of circuit analysis methods. Many of SPICE function have been implemented on a personal computer platform, as described in “The Illustrated Guide to PSPICE®,” by Robert Lamey, which is incorporated herein by reference.
As with Verilog®, the SPICE language has been utilized in many other tools and simulations. In addition, various vendors and groups have attempted to apply similar principles to analog synthesis such as module generators (OPASYN, CADICS, and ADORE from UC Berkeley, and VASE from University of Cincinnati, for example) and topology optimizers (IDAC/ILAC or AutoLinear marketed by Silicon Compiler Systems, AMGIE by Leuven, ASTRX/OBLX by CMU, for example). However, commercially available tools do not provide true synthesis of analog or mixed analog regardless of the underlying description languages or simulators.